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| ? semiconductor components industries, llc, 2015 september, 2015 ? rev. p0 1 publication order number: ncp4308/d ncp4308 product preview synchronous rectifier controller the ncp4308 is a synchronous rectifier controller for switch mode power supplies. the controller enables high efficiency designs for flyback, quasi resonant flyback and llc topologies. externally adjustable minimum off?time and on?time blanking periods provides flexibility to drive various mosfet package types and pcb layout. a reliable and noise less operation of the sr system is insured due to the self synchronization feature . the ncp4308 also utilizes kelvin connection of the driver to the mosfet to achieve high efficiency operation at full load. the precise turn?off threshold, extremely low turn?off delay time and high sink current capability of the driver allow the maximum synchronous rectification mo sfet conduction time. the high accuracy driver and 5 v gate clamp make it ideally suited for directly driving gan devices. features ? self?contained control of synchronous rectifier in ccm, dcm and qr for flyback or llc applications ? precise true secondary zero current detection ? rugged current sense pin (up to 150 v) ? adjustable minimum on?time ? adjustable minimum off - time with ringing detection ? adjustable maximum on?time for ccm controlling of primary qr controller ? improved robust self synchronization capability ? 8 a / 4 a peak current sink / source drive capability ? operating voltage range up to v cc = 35 v ? gan transistor driving capability (options a and c) ? low startup current consumption ? maximum operation frequency up to 1 mhz ? soic - 8 and dfn?8 (4x4) and wdfn8 (2x2) packages ? these are pb?free devices typical applications ? notebook adapters ? high power density ac/dc power supplies (cell phone chargers) ? lcd tvs ? all smps with high efficiency requirements this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. soic?8 d suffix case 751 marking diagrams 4308x = specific device code x = a, b, c, d or q ex = specific device code x = a, 2, c, d or q a = assembly location l = wafer lot y = year w = work week m = date code = pb?free package 1 8 ncp4308x alyw 1 8 (note: microdot may be in either location) 4308x alyw 1 dfn8 mn suffix case 488af www.onsemi.com see detailed ordering and shipping information on page 26 o f this data sheet. ordering information exm 1 wdfn8 mt suffix case 511at
ncp4308 www. onsemi.com 2 figure 1. typical application example ? llc converter d1 ok1 rtn min_ton min_toff min_ton min_toff figure 2. typical application example ? dcm, ccm or qr flyback converter + + + vbulk flyback +vout gnd ok1 r1 r2 r5 r4 c1 c2 c3 c4 c5 d3 d4 d5 tr1 m1 m2 r3 vcc drv fb cs control circuitry ncp4308 www. onsemi.com 3 figure 3. typical application example ? primary side flyback converter + + + vbulk flyback side controller +vout gnd r1 r2 r7 r6 c1 c2 c3 c7 c10 d3 d4 tr1 m1 m2 primary c4 c5 c6 r3 r4 r5 r8 vcc drv comp cs zcd figure 4. typical application example ? qr converter ? capability to force primary into ccm under heavy loads utilizing max?ton + + + vbulk circuitry +vout gnd ok1 r5 r2 r8 r9 r10 c1 c4 c7 d2 d3 d6 tr1 tr2 m1 m3 ncp4308 r7 d5 d1 r1 r11 r12 m2 d4 r3 r4 r6 c2 c5 c6 c3 vcc drv fb cs zcd control qr ncp4308 www. onsemi.com 4 pin function description ver. a, b, c, d ver. q pin name description 1 1 vcc supply voltage pin 2 2 min_toff adjust the minimum off time period by connecting resistor to ground. 3 3 min_ton adjust the minimum on time period by connecting resistor to ground. 4 4 nc leave this pin opened or tie it to ground. 5 ? nc leave this pin opened or tie it to ground. 6 6 cs current sense pin detects if the current flows through the sr mosfet and/or its body diode. basic turn?off detection threshold is 0 mv. a resistor in series with this pin can decrease the turn off threshold if needed. 7 7 gnd ground connection for the sr mosfet driver, v cc decoupling capacitor and for mini- mum on and off time adjust resistors. gnd pin should be wired directly to the sr mosfet source terminal/soldering point using kelvin connection. dfn8 exposed flag should be connected to gnd 8 8 drv driver output for the sr mosfet ? 5 max_ton adjust the maximum on time period by connecting resistor to ground. minimum on time generator min_ton cs detection 100 a cs min_toff nc cs_on cs_off drv vcc gnd v cc managment uvlo drv out driver v dd v dd cs_reset nc adj elapsed en minimum off time generator adj reset elapsed control logic en figure 5. internal circuit architecture ? ncp4308a, b, c, d ncp4308 www. onsemi.com 5 minimum on time generator min_ton cs detection 100 a cs min_toff max_ton cs_on cs_off drv vcc gnd v cc managment uvlo drv out driver v dd v dd cs_reset nc adj elapsed en minimum off time generator adj reset elapsed control logic en elapsed maximum on time generator en adj figure 6. internal circuit architecture ? ncp4308q (ccm qr) with max_ton ncp4308 www. onsemi.com 6 absolute maximum ratings rating symbol value unit supply voltage v cc ?0.3 to 37.0 v min_ton, min_toff, max_ton input voltage v min_ton , v min_toff , v max_ton ?0.3 to v cc v driver output voltage v drv ?0.3 to 17.0 v current sense input voltage v cs ?4 to 150 v current sense dynamic input voltage (t pw = 200 ns) v cs_dyn ?10 to 150 v min_ton, min_toff, max_ton, input current i min_ton , i min_toff , i max_ton ?10 to 10 ma junction to air thermal resistance, 1 oz 1 in 2 copper area, soic8 r j?a_soic8 160 c/w junction to air thermal resistance, 1 oz 1 in 2 copper area, dfn8 r j?a_dfn8 80 c/w junction to air thermal resistance, 1 oz 1 in 2 copper area, wdfn8 r j?a_wdfn8 160 c/w maximum junction temperature t jmax 150 c storage temperature t stg ?60 to 150 c esd capability, human body model, except pin 6, per jesd22?a114e esd hbm 2000 v esd capability, human body model, pin 6, per jesd22?a114e esd hbm 1000 v esd capability, machine model, per jesd22?a115?a esd mm 200 v esd capability, charged device model, except pin 6, per jesd22?c101f esd cdm 750 v esd capability, charged device model, pin 6, per jesd22?c101f esd cdm 250 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device meets latch?up tests defined by jedec standard jesd78d class i. recommended operating conditions parameter symbol min max unit maximum operating input voltage v cc 35 v operating junction temperature t j ?40 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. ncp4308 www. onsemi.com 7 electrical characteristics ?40 c t j 125 c; v cc = 12 v; c drv = 0 nf; r min_ton = r min_toff = 10 k ; v cs = ?1 to +4 v; f cs = 100 khz, dc cs = 50%, unless otherwise noted. typical values are at t j = +25 c parameter test conditions symbol min typ max unit supply section vcc uvlo (ver. b & c) v cc rising, v cs = 0 v v ccon 8.3 8.8 9.3 v v cc falling, v cs = 0 v v ccoff 7.3 7.8 8.3 vcc uvlo hysteresis (ver. b & c) v cchys 1.0 v vcc uvlo (ver. a, d & q) v cc rising, v cs = 0 v v ccon 4.20 4.45 4.70 v v cc falling, v cs = 0 v v ccoff 3.70 3.95 4.20 vcc uvlo hysteresis (ver. a, d & q) v cchys 0.5 v start?up delay v cc rising from 0 to v ccon + 1 v @ tr = 10 s, v cs = 0 v t start_del 75 125 s current consumption, r min_ton = r min_toff = 0 k c drv = 0 nf, f cs = 500 khz a, c i cc 3.3 4.0 5.6 ma b, d, q 3.8 4.5 6.0 c drv = 1 nf, f cs = 500 khz a, c 4.5 6.0 7.5 b, d, q 7.7 9.0 10.7 c drv = 10 nf, f cs = 500 khz a, c 20 25 30 b, d, q 40 50 60 current consumption no switching, v cs = 0 v, r min_ton = r min_toff = 0 k i cc 1.5 2.0 2.5 ma current consumption below uvlo no switching, v cc = v ccoff ? 0.1 v, v cs = 0 v i cc_uvlo 75 125 a driver output output voltage rise?time c drv = 10 nf, 10% to 90% v drvmax t r 40 55 ns output voltage fall?time c drv = 10 nf, 90% to 10% v drvmax t f 20 35 ns driver source resistance r drv_source 1.2 driver sink resistance r drv_sink 0.5 output peak source current i drv_source 4 a output peak sink current i drv_sink 8 a maximum driver output voltage v cc = 35 v, c drv > 1 nf (ver. b, d and q) v drvmax 9.0 9.5 10.5 v v cc = 35 v, c drv > 1 nf (ver. a, c) 4.3 4.7 5.5 minimum driver output voltage v cc = v ccoff + 200 mv (ver. b) v drvmin 7.2 7.8 8.5 v v cc = v ccoff + 200 mv (ver. c) 4.2 4.7 5.3 v cc = v ccoff + 200 mv (ver. a) 3.6 4.0 4.4 v cc = v ccoff + 200 mv (ver. d, q) 3.8 4.0 4.4 cs input total propagation delay from cs to drv output on v cs goes down from 4 to ?1 v, t f_cs = 5 ns t pd_on 35 60 ns total propagation delay from cs to drv output off v cs goes up from ?1 to 4 v, t r_cs = 5 ns t pd_off 12 23 ns cs bias current v cs = ?20 mv i cs ?105 ?100 ?95 a turn on cs threshold voltage v th_cs_on ?120 ?75 ?40 mv turn off cs threshold voltage guaranteed by design v th_cs_off ?1 0 mv turn off timer reset threshold voltage v th_cs_reset 0.42 0.48 0.54 v cs leakage current v cs = 150 v i cs_leakage 0.4 a ncp4308 www. onsemi.com 8 electrical characteristics ?40 c t j 125 c; v cc = 12 v; c drv = 0 nf; r min_ton = r min_toff = 10 k ; v cs = ?1 to +4 v; f cs = 100 khz, dc cs = 50%, unless otherwise noted. typical values are at t j = +25 c parameter unit max typ min symbol test conditions minimum t on and t off adjust minimum t on time r min_ton = 0 t on_min 35 55 75 ns minimum t off time r min_toff = 0 t off_min 190 245 290 ns minimum t on time r min_ton = 10 k t on_min 0.92 1.00 1.08 s minimum t off time r min_toff = 10 k t off_min 0.92 1.00 1.08 s minimum t on time r min_ton = 50 k t on_min 4.62 5.00 5.38 s minimum t off time r min_toff = 50 k t off_min 4.62 5.00 5.38 s maximum t on adjust maximum t on time v max_ton = 3 v t on_max 4.3 4.8 5.3 s maximum t on time v max_ton = 0.3 v t on_max 41 48 55 s maximum t on output current v max_ton = 0.3 v i max_ton ?105 ?100 ?95 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. ncp4308 www. onsemi.com 9 typical characteristics figure 7. v ccon and v ccoff levels, v cs = 0 v, ver. a, d, q figure 8. v ccon and v ccoff levels, v cs = 0 v, ver. b, c t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 3.7 3.8 3.9 4.1 4.2 4.4 4.6 4.7 100 80 60 40 20 0 ?20 ?40 7.3 7.5 7.7 8.1 8.3 8.7 8.9 9.3 v cc (v) v cc (v) 120 4.0 4.3 4.5 v ccon v ccoff v ccon v ccoff 120 7.9 8.5 9.1 figure 9. current consumption, c drv = 0 nf, f cs = 500 khz, ver. d figure 10. current consumption, v cc = v ccoff ? 0.1 v, v cs = 0 v, ver. d v cc (v) t j ( c) 30 25 35 20 15 10 5 0 0 1 2 3 4 5 6 120 100 60 40 20 0 ?20 ?40 0 20 40 60 80 100 120 figure 11. current consumption, v cc = 12 v, v cs = ?1 to 4 v, f cs = 500 khz, ver. a figure 12. current consumption, v cc = 12 v, v cs = ?1 to 4 v, f cs = 500 khz, ver. d t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 0 5 10 15 20 25 30 100 80 60 40 20 0 ?20 ?40 0 10 20 30 40 50 60 i cc (ma) i cc_uvlo ( a) i cc (ma) i cc (ma) t j = 85 c t j = 55 c t j = 125 c t j = 25 c t j = 0 c t j = ?20 c t j = ?40 c 80 120 c drv = 0 nf c drv = 1 nf c drv = 10 nf c drv = 0 nf c drv = 1 nf c drv = 10 nf 120 ncp4308 www. onsemi.com 10 typical characteristics figure 13. cs current, v cs = ?20 mv figure 14. cs current, v cc = 12 v t j ( c) v cs (v) 100 80 60 40 20 0 ?20 ?40 ?110 ?106 ?104 ?100 ?98 ?96 ?94 ?90 0.8 0.6 0.2 0 ?0.2 ?0.4 ?0.8 ?1.0 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 figure 15. supply current vs. cs voltage, v cc = 12 v figure 16. cs turn?on threshold v cs (v) t j ( c) 3 2 1 0 ?1 ?2 ?3 ?4 0 0.5 1.0 1.5 2.0 2.5 3.0 100 80 60 40 20 0 ?20 ?40 ?150 ?130 ?110 ?90 ?70 ?50 ?30 figure 17. cs turn?off threshold figure 18. cs reset threshold t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0.40 0.45 0.50 0.55 0.60 i cs ( a) i cs (ma) i cc (ma) v th_cs_on (mv) v th_cs_off (mv) v th_cs_reset (v) 120 ?92 ?102 ?108 ?0.6 0.4 1.0 4 t j = 125 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ?20 c t j = ?40 c t j = 125 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ?20 c t j = ?40 c 120 120 100 80 60 40 20 0 ?20 ?40 120 ncp4308 www. onsemi.com 11 typical characteristics figure 19. cs reset threshold figure 20. cs leakage, v cs = 150 v v cc (v) t j ( c) 30 25 20 35 15 10 5 0 0.30 0.35 0.45 0.50 0.60 0.65 0.70 0.80 100 120 60 40 20 0 ?20 ?40 0 20 60 80 120 140 180 200 figure 21. propagation delay from cs to drv output on figure 22. propagation delay from cs to drv output off t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 20 25 30 35 40 50 55 60 100 80 60 40 20 0 ?20 ?40 4 6 10 12 16 18 22 24 v th_cs_reset (v) i cs_leakage (na) t pd_on (ns) t pd_off (ns) 0.40 0.55 0.75 80 40 100 160 120 45 120 8 14 20 tbd figure 23. minimum on?time r min_ton = 0 figure 24. minimum on?time r min_ton = 10 k t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 35 40 45 50 55 60 70 75 100 80 60 40 20 0 ?20 ?40 0.92 0.94 0.96 0.98 1.00 1.04 1.06 1.08 t min_ton (ns) t min_ton ( s) 120 65 120 1.02 ncp4308 www. onsemi.com 12 typical characteristics figure 25. minimum on?time r min_ton = 50 k figure 26. minimum off?time r min_toff = 0 t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 4.6 4.7 4.8 4.9 5.0 5.2 5.3 5.4 100 80 60 40 20 0 ?20 ?40 190 200 220 230 240 260 270 290 figure 27. minimum off?time r min_toff = 10 k figure 28. minimum off?time r min_toff = 50 k t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 0.92 0.94 0.96 1.00 1.02 1.04 1.06 1.08 100 80 60 40 20 0 ?20 ?40 4.6 4.7 4.8 4.9 5.0 5.1 5.3 5.4 figure 29. minimum on?time r min_ton = 10 k figure 30. minimum off?time r min_toff = 10 k v cc (v) v cc (v) 30 25 20 35 15 10 5 0 0.92 0.94 0.96 0.98 1.00 1.02 1.03 1.04 35 30 25 20 15 10 5 0 092 0.94 0.96 0.98 1.00 1.02 1.06 1.08 t min_ton ( s) t min_toff (ns) t min_toff ( s) t min_toff ( s) t min_ton ( s) t min_toff ( s) 120 5.1 120 210 250 280 120 0.98 120 5.2 1.01 1.04 ncp4308 www. onsemi.com 13 typical characteristics figure 31. driver and output voltage, ver. b, d and q figure 32. driver output voltage, ver. a and c t j ( c) t j ( c) 100 80 60 40 20 0 ?20 ?40 9.0 9.2 9.4 9.6 9.8 10.0 10.2 10.4 100 80 60 40 20 0 ?20 ?40 4.3 4.5 4.7 4.9 5.1 5.3 5.5 figure 33. maximum on?time, ver. q figure 34. maximum on?time, v max_ton = 3 v, ver. q v max_ton (v) t j ( c) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 15 20 25 35 45 50 100 80 60 40 20 0 ?20 ?40 4.3 4.4 4.6 4.7 4.8 5.0 5.1 5.3 figure 35. maximum on?time, v max_ton = 0.3 v, ver. q t j ( c) 100 80 60 40 20 0 ?20 ?40 41 43 45 47 49 51 53 55 v drv (v) v drv (v) t max_ton ( s) t max_ton ( s) t max_ton ( s) 120 v cc = 12 v, c drv = 0 nf v cc = 12 v, c drv = 1 nf v cc = 12 v, c drv = 10 nf v cc = 35 v, c drv = 0 nf v cc = 35 v, c drv = 1 nf v cc = 35 v, c drv = 10 nf v cc = 12 v, c drv = 0 nf v cc = 12 v, c drv = 1 nf v cc = 12 v, c drv = 10 nf v cc = 35 v, c drv = 0 nf v cc = 35 v, c drv = 1 nf v cc = 35 v, c drv = 10 nf 120 t j = 125 c t j = 85 c t j = 55 c t j = 25 c t j = 0 c t j = ?20 c t j = ?40 c 10 30 40 120 4.5 4.9 5.2 120 ncp4308 www. onsemi.com 14 application information general description the ncp4308 is designed to operate either as a standalone ic or as a companion ic to a primary side controller to help achieve efficient synchronous rectification in switch mode power supplies. this controller features a high current gate driver along with high?speed logic circuitry to provide appropriately timed drive signals to a synchronous rectification mosfet. with its novel architecture, the ncp4308 has enough versatility to keep the synchronous rectification system efficient under any operating mode . the ncp4308 works from an available voltage with range from 4 v (a, d & q options) or 8 v (b & c options) to 35 v (typical). the wide v cc range allows direct connection to the smps output voltage of most adapters such as notebooks, cell phone chargers and lcd tv adapters. precise turn - off threshold of the current sense comparator together with an accurate offset current source allows the user to adjust for any required turn - off current threshold of the sr mosfet switch using a single resistor . compared to other sr controllers that provide turn - off thresholds in the range of ?10 mv to ?5 mv , the ncp4308 offers a turn - off threshold of 0 mv. when using a low r ds(on) sr (1 m ) mosfet our competition, with a ?10 mv turn off, will turn off with 10 a still flowing through the sr fet, while our 0 mv turn off turns off the fet at 0 a; significantly reducing the turn - off current threshold and improving efficiency. many of the competitor parts maintain a drain source voltage across the mosfet causing the sr mosfet to operate in the linear region to reduce turn?off time. thanks to the 8 a sink current of the ncp4308 significantly reduces turn off time allowing for a minimal drain source voltage to be utilized and efficiency maximized. to overcome false triggering issues after turn - on and turn?off events , the ncp4308 provides adjustable minimum on - time and off - time blanking periods. blanking times can be adjusted independently of ic vcc using external resistors connected to gnd. if needed, blanking periods can be modulated using additional components. an extremely fast turn?off comparator, implemented on the current sense pin, allows for ncp4308 implementation in ccm applications without any additional components or external triggering. an output driver features capability to keep sr transistor closed even when there is no supply voltage for ncp4308. sr transistor drain voltage goes up and down during smps operation and this is transferred through drain gate capacitance to gate and may turn on transistor. ncp4308 uses this pulsing voltage at sr transistor gate (drv pin) and uses it internally to provide enough supply to activate internal driver sink transistor. drv voltage is pulled low (not to zero) thanks to this feature and eliminate the risk of turned on sr transistor before enough v cc is applied to ncp4308. some ic versions include a max_ton circuit that helps a quasi resonant (qr) controller to work in ccm mode when a heavy load is present like in the example of a printer?s motor starting up . current sense input figure 36 shows the internal connection of the cs circuitry on the current sense input. when the voltage on the secondary w inding of the smps reverses, the body diode of m1 starts to conduct current and the voltage of m1?s drain drops approximately to ?1 v. the cs pin sources current of 100 a that creates a voltage drop on the r shift_cs resistor (resistor is optional, we recommend shorting this resistor). once the voltage on the cs pin is lower than v th_cs_on threshold, m1 is turned?on. because of parasitic impedances, significant ringing can occur in the application. to overcome false sudden turn?off due to mentioned ringing, the minimum conduction time of the sr mosfet is activated. minimum conduction time can be adjusted using the r min_ton resistor. ncp4308 www. onsemi.com 15 figure 36. current sensing circuitry functionality the sr mosfet is turned - off as soon as the voltage on the cs pin is higher than v th_cs_off (typically ?0.5 mv minus any voltage dropped on the optional r shift_cs ). for the same ringing reason, a minimum off - time timer is asserted once the v cs goes above v th_cs_reset . the minimum off - time can be externally adjusted using r min_toff resistor . the minimum off?time generator can be re?triggered by min_toff reset comparator if some spurious ringing occurs on the cs input after sr mosfet turn?off event. this feature significantly simplifies sr system implementation in flyback converters. in an llc converter the sr mosfet m1 channel conducts while secondary side current is decreasing (refer to figure 37) . therefore the turn?off current depends on mosfet r dson . the ?0.5 mv threshold provides an optimum switching period usage while keeping enough time margin for the gate turn - off . the r shift_cs resistor provides the designer with the possibility to modify (increase) the actual turn?on and turn?off secondary current thresholds . to ensure proper switching, the min_t off timer is reset, when the v ds of the mosfet rings and falls down past the v th_cs_reset . the minimum off?time needs to expire before another drive pulse can be initiated. minimum off?time timer is started again when v ds rises above v th_cs_reset . ncp4308 www. onsemi.com 16 v ds =v cs v th_cs _reset ?(r shift _cs *i cs ) v th_cs_off ?(r shift _cs *i cs ) v th_cs _on ?(r shift _cs *i cs ) v drv min on? time t min off? time min t off timer was stopped here because of v cs ncp4308 www. onsemi.com 18 figure 40. waveforms from sr system implemented in llc application and using mosfet in to220 package with long leads ? sr mosfet channel conduction time is reduced note that the ef ficiency impact caused by the error voltage due to the parasitic inductance increases with lower mosfets r ds(on) and/or higher operating frequency . it is thus beneficial to minimize sr mosfet package leads length in order to maximize application ef ficiency. the optimum solution for applications with high secondary current i/ t and high operating frequency is to use lead?less sr mosfet i.e. sr mosfet in smt package. the parasitic inductance of a smt package is negligible causing insignificant cs turn?off threshold shift and thus minimum impact to efficiency (refer to figure 41). ncp4308 www. onsemi.com 19 figure 41. waveforms from sr system implemented in llc application and using mosfet in smt package with minimized parasitic inductance ? sr mosfet channel conduction time is optimized it can be deduced from the above paragraphs on the induced error voltage and parameter tables that turn?off threshold precision is quite critical. if we consider a sr mosfet with r ds(on) of 1 m , the 1 mv error voltage on the cs pin results in a 1 a turn - off current threshold difference; thus the pcb layout is very critical when implementing the sr system. note that the cs turn - off comparator is referred to the gnd pin. any parasitic impedance (resistive or inductive ? even on the magnitude of m and nh values) can cause a high error voltage that is then evaluated by the cs comparator. ideally the cs turn?off comparator should detect voltage that is caused by secondary current directly on the sr mosfet channel resistance. in reality there will be small parasitic impedance on the cs path due to the bonding wires, leads and soldering. to assure the best ef ficiency results , a kelvin connection of the sr controller to the power circuitry should be implemented. the gnd pin should be connected to the sr mosfet source soldering point and current sense pin should be connected to the sr mosfet drain soldering point ? refer to figure 39 . using a kelvin connection will avoid any impact of pcb layout parasitic elements on the sr controller functionality; sr mosfet parasitic elements will still play a role in attaining an error voltage. figure 42 and figure 43 show examples of sr system layouts using mosfets in to220 and smt packages . it is evident that the mosfet leads should be as short as possible to minimize parasitic inductances when using packages with leads (like to220). figure 43 shows how to layout design with two sr mosfet s in parallel. it has to be noted that it is not easy task and designer has to paid lot of attention to do symmetric kelvin connection. figure 42. recommended layout when using sr mosfet in to220 package figure 43. recommended layout when using sr mosfet in smt package (2x so8 fl) ncp4308 www. onsemi.com 20 figure 44. ncp4308 operation after start?up event v ds = v cs v th_cs_reset v th_cs_off v th_cs_on v ccon min off? time v drv v cc min on?time t min_toff t min_toff t min_ton not complete t min_toff ? > ic is not activated complete t min_toff activates ic t min_toff is stopped due to v ds drops below v th_cs_reset t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 self synchronization self synchronization feature during start?up can be seen at figure 44. figure 44 shows how the minimum of f?time timer is reset when cs voltage is oscillating through v th_cs_reset level. the ncp4308 starts operation at time t1. internal logic waits for one complete minimum off?time period to expire before the ncp4308 can activate the driver after a start?up event. the minimum off?time timer starts to run at time t1, because v cs is higher than v th_cs_reset . the timer is then reset , before its set minimum of f?time period expires, at time t2 thanks to cs voltage lower than v th_cs_reset threshold. the aforementioned reset situation can be seen again at time t3, t4, t5 and t6. a complete minimum off?time period elapses between times t7 and t8 allowing the ic to activate a driver output after time t8. minimum t on and t off adjustment the ncp4308 offers an adjustable minimum on?time and off?time blanking periods that ease the implementation of a synchronous rectification system in any smps topology. these timers avoid false triggering on the cs input after the mosfet is turned on or off. the adjustment of minimum t on and t off periods are done based on an internal timing capacitance and external resistors connected to the gnd pin ? refer to figure 45 for a better understanding. ncp4308 www. onsemi.com 21 figure 45. internal connection of the min_ton generator (the min_toff works in the same way) current through the min_ton adjust resistor can be calculated as: i r_min_ton v ref r min_ton (eq. 5) if the internal current mirror creates the same current through r min_ton as used the internal timing capacitor (ct) charging, then the minimum on?time duration can be calculated using this equation. t min_ton c t v ref i r_min_ton c t v ref v ref r min_ton c t r min_to n (eq. 6) the internal capacitor size would be too large if i r_min_ton was used. the internal current mirror uses a proportional current, given by the internal current mirror ratio. one can then calculate the min_ton and min_toff blanking periods using below equations: t min_ton 1.00 * 10 ?4 *r min_ton [ s] (eq. 7) t min_toff 1.00 * 10 ?4 *r min_toff [ s] (eq. 8) note that the internal timing comparator delay affects the accuracy of equations 7 and 8 when min_ton/ min_toff times are selected near to their minimum possible values. please refer to figures 46 and 47 for measured minimum on and off time charts. figure 46. min_ton adjust characteristics r min_ton (k ) 90 60 50 40 30 20 10 0 0 1 2 4 5 6 7 10 t min_ton ( s) 100 3 80 70 8 9 figure 47. min_toff adjust characteristics r min_toff (k ) 90 60 50 40 30 20 10 0 0 1 2 4 5 6 7 10 t min_toff ( s) 100 3 80 70 8 9 ncp4308 www. onsemi.com 22 the absolute minimum t on duration is internally clamped to 55 ns and minimum t off duration to 245 ns in order to prevent any potential issues with the min_ton and/or min_toff pins being shorted to gnd. the ncp4308 features dedicated anti?ringing protection system that is implemented with a min_toff blank generator. the minimum off?time one?shot generator is restarted in the case when the cs pin voltage crosses v th_cs_reset threshold and min_toff period is active. the total off - time blanking period is prolonged due to the ringing in the application (refer to figure 37) . some applications may require adaptive minimum on and off time blanking periods. with ncp4308 it is possible to modulate blanking periods by using an external npn transistor ? refer to figure 48. the modulation signal can be derived based on the load current, feedback regulator voltage or other application parameter . figure 48. possible connection for min_t on and min_t off modulation maximum t on adjustment the ncp4308q offers an adjustable maximum on?time (like the min_t on and min_t off settings shown above) that can be very useful for qr controllers at high loads. under high load conditions the qr controller can operate in ccm thanks to this feature. the ncp4308q version has the ability to turn?off the drv signal to the sr mosfet before the secondary side current reaches zero. the drv signal from the ncp4308q can be fed to the primary side through a pulse transformer (see figure 4 for detail) to a transistor on the primary side to emulate a zcd event before an actual zcd event occurs. this feature helps to keep the minimum switching frequency up so that there is better ener gy transfer through the transformer (a smaller transformer core can be used). also another advantage is that the ic controls the sr mosfet and turns off from secondary side before the primary side is turned on in ccm to ensure no cross conduction. by controlling the sr mosfet?s turn off before the primary side turn off, producing a zero cross conduction operation, this will improve efficiency. the internal connection of the max_ton feature is shown in figure 49. figure 49 shows a method that allows for a modification of the maximum on?time according to output voltage. at a lower v out , caused by hard overload or at startup, the maximum on?time should be longer than at nominal voltage. resistor r a can be used to modulate maximum on?time according to v out or any other parameter. the operational waveforms at heavy load in qr type smps are shown in figure 50. after t max_ton time is exceeded, the synchronous switch is turned off and the secondary current is conducted by the diode. information about turned off sr mosfet is transferred by the drv pin through a small pulse transformer to the primary side where it acts on the zcd detection circuit to allow the primary switch to be turned on. secondary side current disappears before the primary switch is turned on without a possibility of cross current condition. ncp4308 www. onsemi.com 23 figure 49. internal connection of the max_ton generator, ncp4308q v ds =v cs v th_cs _reset ?(r shift _cs *i cs ) v th_cs_off ?(r shift _cs *i cs ) v th_cs _on ?(r shift _cs *i cs ) v drv min on? time t min off? time t min _ton t min _toff i sec the t min _ton and t min _toff are adjustable by r min _ton and r min _toff resistors, t max_ton is adjustable by r max_ton turn?on delay turn ? off delay primary virtual zcd detection delay max on? time t max _ton figure 50. function of max_ton generator in heavy load condition ncp4308 www. onsemi.com 24 power dissipation calculation it is important to consider the power dissipation in the mosfet driver of a sr system. if no external gate resistor is used and the internal gate resistance of the mosfet is very low, nearly all energy losses related to gate charge are dissipated in the driver. thus it is necessary to check the sr driver power losses in the target application to avoid over temperature and to optimize efficiency. in sr systems the body diode of the sr mosfet starts conducting before sr mosfet is turned?on , because there is some delay from v th_cs_on detect to turn?on the driver. on the other hand , the sr mosfet turn off process always starts before the drain to source voltage rises up significantly. therefore , the mosfet switch always operates under zero voltage switching (zvs) conditions when in a synchronous rectification system. the following steps show how to approximately calculate the power dissipation and die temperature of the ncp4308 controller. note that real results can vary due to the effects of the pcb layout on the thermal resistance. step 1 ? mosfet gate?to source capacitance: during zvs operation the gate to drain capacitance does not have a miller effect like in hard switching systems because the drain to source voltage does not change (or its change is negligible). figure 51. typical mosfet capacitances dependency on v ds and v gs voltages c iss c gs c gd c rss c gd c oss c ds c gd therefore, the input capacitance of a mosfet operating in zvs mode is given by the parallel combination of the gate to source and gate to drain capacitances (i.e. c iss capacitance for given gate to source voltage). the total gate charge , q g_total , of most mosfets on the market is defined for hard switching conditions. in order to accurately calculate the driving losses in a sr system, it is necessary to determine the gate charge of the mosfet for operation specifically in a zvs system. some manufacturers define this parameter as q g_zvs . unfortunately , most datasheets do not provide this data. if the c iss (or q g_zvs ) parameter is not available then it will need to be measured . please note that the input capacitance is not linear (as shown figure 51) and it needs to be characterized for a given gate voltage clamp level. step 2 ? gate drive losses calculation: gate drive losses are affected by the gate driver clamp voltage. gate driver clamp voltage selection depends on the type of mosfet used (threshold voltage versus channel resistance). the total power losses (driving loses and conduction losses) should be considered when selecting the gate driver clamp voltage. most of today?s mosfets for sr systems feature low r ds(on) for 5 v v gs voltage. the ncp4308 offers both a 5 v gate clamp and a 10 v gate clamp for those mosfet that require higher gate to source voltage . the total driving loss can be calculated using the selected gate driver clamp voltage and the input capacitance of the mosfet: p drv_total v cc v clamp c g_zvs f sw (eq. 9) where: v cc is the ncp4308 supply voltage v clamp is the driver clamp voltage c g_zvs is the gate to source capacitance of the mosfet in zvs mode f sw is the switching frequency of the target application the total driving power loss won?t only be dissipated in the ic , but also in external resistances like the external gate resistor (if used) and the mosfet internal gate resistance (figure 50). because ncp4308 features a clamped driver, it?s high side portion can be modeled as a regular driver switch with equivalent resistance and a series voltage source. the low side driver switch resistance does not drop immediately at turn?off, thus it is necessary to use an equivalent value (r drv_sin_eq ) for calculations. this method simplifies power losses calculations and still provides acceptable accuracy. internal driver power dissipation can then be calculated using equation 10: ncp4308 www. onsemi.com 25 figure 52. equivalent schematic of gate drive circuitry p drv_ic 1 2 c g_zvs v clamp 2 f sw r drv_sink_eq r drv_sink_eq r g_ext r g_int c g_zvs v clamp f sw v cc v clamp 1 2 c g_zvs v clamp 2 f sw r drv_source_eq r drv_source_eq r g_ext r g_int (eq. 10) where: r drv_sink_eq is the ncp4308x driver low side switch equivalent resistance (0.5 ) r drv_source_eq is the ncp4308x driver high side switch equivalent resistance (1.2 ) r g_ext is the external gate resistor (if used) r g_int is the internal gate resistance of the mosfet step 3 ? ic consumption calculation: in this step , power dissipation related to the internal ic consumption is calculated. this power loss is given by the i cc current and the ic supply voltage. the i cc current depends on switching frequency and also on the selected min t on and t off periods because there is current flowing out from the min t on and t off pins. the most accurate method for calculating these losses is to measure the i cc current when c drv = 0 nf and the ic is switching at the target frequency with given min_ton and min_toff adjust resistors. ic consumption losses can be calculated as: p cc v cc i cc (eq. 11) step 4 ? ic die temperature arise calculation: the die temperature can be calculated now that the total internal power losses have been determined (driver losses plus internal ic consumption losses). the package thermal resistance is specified in the maximum ratings table for a 35 m thin copper layer with no extra copper plates on any pin (i.e. just 0.5 mm trace to each pin with standard soldering points are used). the die temperature is calculated as: t die p drv_ic p cc r j?a t a (eq. 12) where: p drv_ic is the ic driver internal power dissipation p cc is the ic control internal power dissipation r ja is the thermal resistance from junction to ambient t a is the ambient temperature ncp4308 www. onsemi.com 26 product options opn package uvlo [v] drv clamp [v] pin 5 function usage ncp4308adr2g soic8 4.5 4.7 nc llc, ccm flyback, dcm flyback, qr, qr with primary side ccm control ncp4308amttwg wdfn8 4.5 4.7 nc ncp4308ddr2g soic8 4.5 9.5 nc ncp4308dmntwg dfn8 4.5 9.5 nc ncp4308dmttwg wdfn8 4.5 9.5 nc NCP4308QDR2G soic8 4.5 9.5 max_ton qr with forced ccm from secondary side ordering information device package package marking packing shipping ? ncp4308adr2g soic8 ncp4308a soic?8 (pb?free) 2500 /tape & reel ncp4308ddr2g ncp4308d NCP4308QDR2G ncp4308q ncp4308amttwg wdfn8 ea wdfn?8 (pb?free) 3000 /tape & reel ncp4308dmttwg ed ncp4308dmntwg dfn8 4308d dfn?8 (pb?free) 4000 /tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncp4308 www. onsemi.com 27 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* ncp4308 www. onsemi.com 28 package dimensions dfn8 4x4 case 488af issue c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 4.00 bsc d2 1.91 2.21 e 4.00 bsc e2 2.09 2.39 e 0.80 bsc k 0.20 ??? l 0.30 0.50 d b e c 0.15 a c 0.15 2x 2x top view side view bottom view ?? ? ? ? ? ? ? c 0.08 c 0.10 ? ? ? ? ? e 8x l k e2 d2 b note 3 1 4 5 8 8x 0.10 c 0.05 c ab pin one reference *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8x 0.63 2.21 2.39 8x 0.80 pitch 4.30 0.35 l1 detail a l optional constructions ??? ?? ?? ??? 0.15 detail b note 4 detail a dimensions: millimeters package outline ncp4308 www. onsemi.com 29 package dimensions seating plane d e 0.10 c a3 a a1 0.10 c wdfn8 2x2, 0.5p case 511at issue o dim a min max millimeters 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d e e l pin one reference 0.05 c 0.05 c a 0.10 c note 3 l2 e b b 4 8 8x 1 5 0.05 c l1 2.00 bsc 2.00 bsc 0.50 bsc 0.40 0.60 --- 0.15 bottom view l 7x l1 detail a l alternate terminal constructions l l2 0.50 0.70 b top view side view notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.78 7x dimensions: millimeters 0.30 pitch 8x 1 package outline recommended 0.88 2x 2x 8x e/2 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp4308/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative |
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